AEIF 2026: Julin Tech’s Junyong Deng on the "Quantification Gap" in Automotive-Grade Chip SI/PI Simulation

The AEIF (Automotive Electronics Innovation Forum) took place in Shanghai on May 20–21, focusing on the electrification of intelligent driving, chip toolchains, and ecosystem security. The forum gathered key enterprises from across the automotive supply chain, including vehicle manufacturers, component suppliers, automotive chip designers, and AI/Internet software firms.

Junyong Deng, Vice General Manager of Julin Technology, was invited to deliver a keynote speech titled "SI/PI Simulation Challenges for High-Performance Automotive Chips." Deng systematically dissected the structural challenges in Signal Integrity (SI) and Power Integrity (PI) design verification driven by the "New Four Modernizations" (electrification, intelligence, connectivity, and sharing) of the automotive industry, while sharing Julin Tech’s R&D path in simulation algorithms.

I. At the Intersection of "Consumer Performance" and "Industrial Reliability"

Deng noted that the automotive industry is evolving toward high-performance computing. Applications like ADAS (Advanced Driver Assistance Systems), intelligent cockpits, and central computing units are introducing 7nm/5nm process nodes, 2.5D/3D packaging, and Chiplet technology to the automotive sector.

"The computing requirements for autonomous driving are pushing automotive chips toward parity with industrial and consumer-grade performance chips," said Deng. "However, automotive standards mandate wide temperature ranges (-40℃ to 150℃), 15+ year lifespans, and strict ASIL functional safety compliance—constraints that are virtually non-existent in consumer scenarios." This convergence makes SI/PI simulation exponentially more difficult than in previous generations.

II. The "Quantification Gap" in Automotive Standards

Deng argued that mainstream automotive standards cover SI/PI only indirectly:

• AEC-Q100 focuses on post-package mechanical failure, not SI/PI metrics.

• ISO 26262 (Functional Safety) uses hardware failure metrics (PMHF, SPFM, LFM) that are indirectly affected by SI/PI, but lacks direct constraints.

• CISPR 25 (EMC/EMI) reolates to SI/PI design quality but provides no direct sign-off metrics.

"Automotive-grade requirements for SI/PI are largely unquantified, forcing companies to follow 'strict' internal guidelines that lack an industry-wide benchmark," Deng summarized. "Without clear signoff standards, every company is effectively deciding based on its own proprietary judgment."

III. The Accuracy-Efficiency Dilemma in Signoff

Deng analyzed the core conflicts in current high-speed interface sign-off processes:

• Statistical Analysis: High speed, but lacks accuracy in handling non-linear effects like crosstalk.

• Bit-by-Bit Simulation: Supports adaptive equalization but struggles with low-BER extrapolation.

• Full Transient Simulation: Highest accuracy, including power noise, but extremely slow and limited in jitter/BER calculation.

Julin Tech is advocating a "Return to Transient" approach: combining Full Transient simulation with EQ post-processing to maximize efficiency by using the "worst-case pattern." Additionally, Julin is developing Transient-based BER Contour workflows, which provide transient-level precision with minimized pattern counts. Comparative data presented by Deng showed that traditional statistical analysis was consistently overly pessimistic, whereas Julin’s transient-based verification yielded highly consistent results.

IV. From "Simulation Pass" to "Mass Production Yield": Introducing DFQ

Beyond algorithm accuracy, process manufacturing deviation is a critical variable. Deng introduced the DFQ (Design for Quality) feature within SIDesigner.

In a DDR design case study, he showed two schemes:

• Scheme A: Larger eye-diagram margin (70.3mV height / 26.3ps width).

• Scheme B: Slightly tighter margin (69.9mV height / 25.8ps width).

However, after applying DFQ analysis to account for process fluctuations, Scheme A had a defect rate of 13.8%, while Scheme B was reduced to just 7.6%. "A good simulation result is not the same as a good product," Deng emphasized. "Once parameter distribution is considered, the ranking of schemes can completely flip."

V. Three Recommendations for the Industry

Deng proposed three strategic suggestions:

1. Standardize Metrics: Automotive standards should introduce clear SI/PI design and test metrics to support systematic quality assurance, especially for Chiplet architectures.

2. Enhance EDA Capabilities: Tools must offer systematic support for "extreme conditions" (high heat, aging, noise coupling) without requiring engineers to build manual simulation environments.

3. Strengthen Ecosystem Feedback: EDA vendors must refine core algorithms, while chip design firms must provide real-world scenarios to create a closed-loop feedback system.

About SIDesigner

SIDesigner is Julin Technology's one-stop platform for high-speed SI/PI circuit-level simulation. Key features include:

• SIDCore Engine: Integrated True-SPICE and Channel Simulation (Golden Standard precision).

• Broad Support: Full-scene sign-off for high-speed parallel interfaces (DDR, HBM, UCIe) and SerDes (PCIe, MIPI, USB).

• Advanced Modules: Built-in DFQ, PDA, BERC, and RS-Code simulation for process deviation analysis, worst-case pattern estimation, and FEC error correction verification.