AEIF 2026: Julin Tech’s Beijie Qian on Why "Simulation Pass" Does Not Equal "Mass Production Yield"

On May 21, at the AEIF Automotive Electronics Innovation Forum sub-forum regarding automotive-grade chip industrialization and ecosystem synergy, Beijie Qian, Sales Director at Julin Technology, delivered a keynote speech titled "Challenges and Solutions for High-Speed Signal Simulation in Automotive-Grade Chips."

Qian opened the presentation with a compelling data set comparing two DDR design schemes:

• Scheme A: Eye height 70.3mV / Eye width 26.3ps. Traditional Sign-off criteria favored this scheme due to its larger margin.

• Scheme B: Eye height 69.9mV / Eye width 25.8ps. Initially viewed as a secondary option due to slightly smaller margins.

  
  

However, when production process deviations were integrated into the analysis, the conclusions were completely reversed:

• Scheme A Mass Production Defect Rate: 13.8%

• Scheme B Mass Production Defect Rate: 7.6%

  
  

"This is not an isolated case," Qian noted. "We repeatedly see the same scenario with leading IC design clients: simulations pass, but mass production yields fail to meet expectations. This gap is a hidden commercial risk often overlooked in automotive-grade chip design processes."

I. Where the Disconnect Begins

The disconnect stems from two structural assumptions in traditional simulation processes:

Assumption 1: Process parameters are fixed. Traditional simulations rely on nominal process conditions using typical values for resistance, capacitance, and routing parameters. In reality, wafers and PCBs fluctuate within tolerance ranges. For high-speed interfaces with tight margins, these fluctuations determine whether a chip is a "good die" or a failure.

Assumption 2: Statistical analysis is inherently trustworthy. High-speed parallel interface Sign-off commonly relies on Channel Simulation (Statistical analysis). However, this method harbors systemic errors when handling non-linear effects such as crosstalk and noise, often yielding overly pessimistic results.

Designers essentially approve designs under two layers of uncertainty: ideal reference conditions and inaccurate judgment metrics, compressing risk until it manifests during mass production.

II. Yield is Profit: Bringing Yield Goals into the Design Phase

Scheme B’s ability to achieve a 7.6% defect rate is attributed to the DFQ (Design for Quality) feature in SIDesigner.

Proactive Quality: DFQ accounts for the statistical distribution of process parameters during the design stage.

Advanced Modeling: Through DOE (Design of Experiments) and RSM (Response Surface Methodology), it constructs high-precision predictive models.

Monte Carlo Analysis: By simulating real-world production conditions, DFQ shifts the focus from "nominal performance" to "yield stability".

Simulation is no longer just a "pass/fail" gate; it is a predictive tool for tape-out decisions, forecasting where defect rates will actually land on the production line.

III. Accuracy as the Foundation

DFQ’s effectiveness relies on high simulation accuracy; otherwise, yield prediction only compounds existing errors. Julin Technology has focused on the following:

SIDCore Engine: Integrates both Golden-precision True-SPICE and Channel Simulation.

"Back to Transient" Path: By combining Full Transient simulation with EQ post-processing and developing Transient BER contour workflows, Julin provides transient-level precision with improved practicality.

Systemic Alignment: Verification shows that traditional statistical analysis was consistently overly pessimistic, whereas Julin's transient-based results were highly consistent, proving the errors stemmed from the statistical algorithms themselves.

IV. Recommendations for Design Teams

Qian concluded with three recommendations for design teams:

• Prioritize Yield Goals: Move yield discussions to the design stage. The earlier an adjustment is made, the lower the cost; late-stage discovery leads to exponential costs.

• Establish Internal Standards: With few quantitative requirements for SI/PI in automotive standards, companies should leverage real project data to build repeatable, rigorous internal standards.

• Create a Feedback Loop: Simulation tools should be integrated into a design feedback loop rather than serving only as a validation step. Continuous interaction between design teams and tool providers is vital in the high-stakes automotive sector.

About SIDesigner

SIDesigner is Julin Technology's one-stop platform for high-speed SI/PI circuit-level simulation, covering the entire link from chip to package to system. Its core engine, SIDCore, integrates Golden-precision True-SPICE and Channel Simulation, supporting full-scene sign-off for high-speed parallel interfaces (DDR/HBM/UCIe) and SerDes (PCIe/MIPI/USB). It includes advanced features like DFQ, PDA, BERC, and RS-Code for process deviation analysis and worst-case pattern estimation.